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high performance, 3.2 ghz, 14-output fanout buffer data sheet HMC7043 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015C2016 analog devices, inc. all rights reserved. technical support www.analog.com features jedec jesd204b support low additive jitter: <15 fs rms at 2457.6 mhz (12 khz to 20 mhz) very low noise floor: ?155.2 dbc/hz at 983.04 mhz up to 14 lvds, lvpecl, or cml type device clocks (dclks) maximum clkoutx/ clkoutx and sclkoutx/ sclkoutx frequency of 3200 mhz jesd204b-compatible system reference (sysref) pulses 25 ps analog and ? clock input cycle digital delay independently programmable on each of 14 clock output channels spi-programmable adjustable noise floor vs. power consumption sysref valid interrupt to simplify jesd204b synchronization supports deterministic synchronization of multiple HMC7043 devices rfsyncin pin or spi-controlled sync trigger for output synchronization of jesd204b gpio alarm/status indicator to determine system health clock input to support up to 6 ghz 48-lead, 7 mm 7 mm lfcsp package applications jesd204b clock generation cellular infrastructure (multicarrier gsm, lte, w-cdma) data converter clocking phase array reference distribution microwave baseband cards general description the HMC7043 is a high performance clock buffer for the distribution of ultralow phase noise references for high speed data converters with either parallel or serial (jesd204b type) interfaces. the HMC7043 is designed to meet the requirements of multicarrier gsm and lte base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. the HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (bts) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (fpgas), and digital front-end asics. the HMC7043 can generate up to seven dclk and sysref clock pairs per the jesd204b interface requirements. the system designer can generate a lower number of dclk and sysref pairs, and configure the remaining output signal paths for independent phase and frequency. both the dclk and sysref clock outputs can be configured to support different signaling standards, including cml, lvds, lvpecl, and lvcmos, and different bias conditions to adjust for varying board insertion losses. one of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. all 14 channels feature both frequency and phase adjustment. the outputs can also be programmed for 50 or 100 internal and external termination options. the HMC7043 device features an rf sync feature that synchro- nizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. this operation is achieved by rephrasing the nested HMC7043 or sysref control unit/divider, deterministically, and then restarting the output dividers with this new phase. the HMC7043 is offered in a 48-lead, 7 mm 7 mm lfcsp package with an exposed pad connected to ground. functional block diagram clkin/ clkin rfsyncin/ rfsyncin 13114-001 sdata spi control interface slen sclk 14-clock distribution sysref control clkout0 clkout0 sclkout1 sclkout1 clkout12 clkout12 sclkout13 sclkout13 figure 1.
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HMC7043 data sheet rev. b | page 2 of 43 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 conditions ..................................................................................... 3 supply current .............................................................................. 3 digital input/output (i/o) electrical specifications ............... 4 clock input path specifications .................................................. 4 additive jitter and phase noise characteristics ....................... 5 clock output distribution specifications ................................. 5 clock output driver characteristics ......................................... 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 typical application circuits .......................................................... 13 terminology .................................................................................... 14 theory of operation ...................................................................... 15 detailed block diagram ............................................................ 16 clock input network ................................................................. 16 clock output network .............................................................. 17 typical programming sequence ............................................... 23 power supply considerations ................................................... 24 serial control port ......................................................................... 27 serial port interface (spi) control ........................................... 27 control registers ............................................................................ 28 control register map ................................................................ 28 control register map bit descriptions ................................... 33 applications information .............................................................. 41 evaluation pcb and schematic ............................................... 41 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43 revision history 7/2016 rev. a to rev. b changes to table 1 ............................................................................ 3 5 / 20 1 6 rev. 0 to rev. a changes to table 3 ............................................................................. 4 change to maximum operating frequency parameter , table 7 ..... 7 added figure 6, renumbered sequentially ................................ 11 change to synchronization fsm/pulse generator timing section ................................................................................. 21 changes to table 20 ........................................................................ 2 8 change to table 22 ......................................................................... 33 changes to table 28 ........................................................................ 3 4 changes to table 29 ........................................................................ 3 5 change to table 31 ......................................................................... 3 6 change to table 38 ......................................................................... 3 7 changes to table 41 ........................................................................ 39 1 2 / 20 15 revision 0 : initial version
data sheet HMC7043 rev. b | page 3 of 43 specifications v cc = 3.3 v 5%, and t a = 25c, unless otherwise noted. minimum and maximum values are given over the full v cc and t a (?40c to +85c) variation, as listed in table 1. conditions table 1. parameter 1 min typ max unit test conditions/comments supply voltage, v cc vcc1_clkdist 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for clk distribution vcc2_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 2 and output channel 3 vcc3_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 4, output channel 5, output channel 6 and output channel 7 vcc4_clkin 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for the clock input path vcc5_sysref 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for the common sysref divider vcc6_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 8, output channel 9, output channel 10, and output channel 11 vcc7_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 0, output channel 1, output channel 12, and output channel 13 temperature ambient temperature range, t a ?40 +25 +85 c 1 maximum values are guaranteed by design and characterization. supply current for detailed test conditions, see table 17 and table 18. table 2 parameter 1, 2 min typ max unit test conditions/comments current consumption 3 vcc1_clkdist 87 125 ma vcc2_out 4 90 250 ma typical value is given at t a = 25c with two lvds clocks at divide by 8 vcc3_out 4 52 500 ma typical value is given at 25c with two lvds high performance clocks, fundamental frequency of the clock input (f o ), two sysref clocks (off ) vcc4_clkin 16 25 ma typical value is given at t a = 25c with rf synchronization (rfsync) input buffer off vcc5_sysref 23 35 ma typical value is given at t a = 25c with internal rf sync path off vcc6_out 4 90 500 ma typical value is given at 25c with two lvds high performance clocks at divide by 2, two sysref clocks (off ) vcc7_out 4 100 500 ma typical value is given at 25c with two lvds clocks at divide by 8, two sysref clocks (off ) total current 458 ma 1 maximum values are guaranteed by design and characterization. 2 currents include lvds termination currents. 3 maximum values are for all circuits enabled in their worst case power consumption mode, pvt var iations, and accounting for pea k current draw during temporary synchronization events. 4 typical specification applies to a normal usage profile (profile 1 in table 17) but very low duty cycle currents (sync events) and some optional features are disabled. this specification assumes output configurations as descri bed in the test condit ions/comments column.
HMC7043 data sheet rev. b | page 4 of 43 digital input/output ( i/o ) electrical specifica tions table 3 . parameter min typ max unit test conditions/comments digital input si gnals (reset, slen, sclk ) safe input voltage range ? 0.1 + 3.6 v input load 0.3 pf input voltage input logic high 1.2 v cc v input logic low 0 0.5 v spi bus frequency 10 mhz digital bidirectional signals configured as inputs (sdata, gpio ) safe input voltage range ?0.1 +3.6 v input capacitance 0.4 pf input resistance 50 g ? input voltage input logic high 1.22 v cc v input logic low 0 0.24 v input hysteresis 0.2 v occurs around 0.85 v gpio al arm muxing / delay delay from internal alarm/signal to general - purpose output ( gpo ) driver 2 ns does not include t dgpo digital bidirectional signals confifured as outputs (sdata, gpio) cmos m ode logic 1 level 1.6 1.9 2.2 v logic 0 level 0 0.1 v output drive resistance (r drive ) 50 ? output driver delay (t dgpo ) 1.5 + 42 c load ns approximately 1.5 ns + 0.69 r drive c load (c l oad in nf) maximum supported dc current 1 0.6 ma o pen -d rain m ode external 1 k? p ull -up resistor logic 1 level 3.6 v 3.6 v maximum permitted ; specifications s et by external supply logic 0 level 0.13 0.28 v against a 1 k ? external pull - up resistor to 3.3 v pull - down impedance 60 ? maximum supported sink current 1 5 ma 1 guaranteed by design and characterization for long - term reliability. clock input path specifications table 4 . parameter min typ max unit test conditions /comments clk input (clkin) characteristics re commended input power, ac - coupled differential ?6 + 8 dbm single - ended 1 ?10 + 6 dbm noise floor degrade by 3 db at f clkin = 2400 mhz retu rn loss ?12 db when terminated with 100 ? differential clock i nput frequency ( f clkin ) 200 3200 mhz fundamental mode; if < 1 ghz, set the low frequency clock input path enable bit (register 0x0064, bit 0) 200 6000 mhz using clock input 2 comm on - mode range 0.4 2. 4 v 1 guaranteed by design and characterization.
data sheet HMC7043 rev. b | page 5 of 43 additive jitter and p hase noise characteristics table 5 . parameter 1 min typ max unit test conditions/comments additive jitter hmc7044 used as a clock source (see figure 3 ) rms additive jitter <30 fs rms clock output frequency ( f clkout ) = 983.04 mhz, bw = 12 khz to 20 mhz , clock input slew rate 8 ns <15 fs rms f clkout = 2457.6 mhz, bw = 12 khz to 20 mhz , clock input slew rate 4 ns clock output phase noise hmc830 used as a clock source and configured to produce 983.04 mhz at the output (see figure 4 ) , i nput slew rate > 1 v/ns absolute phase noise offset = 1 mhz ? 144.3 dbc/hz f clkout = 983.04 mhz, f clkout = 983.04 mhz, divide by 1 at the output offset = 10 mhz ? 154.8 dbc/hz f clkout = 983.04 mhz, f clkout = 2949.12 mhz, divide by 3 at the output offset = 20 mhz ? 155. 2 dbc/hz f clkout = 983.04 mhz, f clkout = 983.04 mhz, divide by 1 at the output 1 guaranteed by design and characterization. clock output distrib ution specifications table 6 . parameter min typ max unit test conditions/comments clock output skew clkoutx/ clkoutx to sclkoutx/ sclkoutx skew w ithin one clock output pair 15 |ps| same pair, same type termination and configuration any clkoutx/ clkoutx to any sclkoutx/ sclkoutx 30 |ps| any pair, same type termination and configuration propagation delay clkin to clkoutx and sclkoutx 1 770 820 870 ps f clkin = 983.04 mhz, all v cc set to 3.3 v clock o utpu t d ivider c haracteristics 12-b it divider range 1 4094 1, 3, 5, and all even numbers up to 4094 sysref cloc k output divider characteristics 12-b it divider range 1 4094 1, 3, 5 , and all even numbers up to 4094; pulse generator behavior is only supported for divide ratios 32 clock output analog fine delay analog fine delay adjustment range 1 135 670 ps 24 delay steps, f clkout = 983.04 mhz resolution 25 ps f clkout = 983.04 mhz (2949.12 mhz/3) maxi mum analog fine delay frequency 1600 mhz cloc k output coarse delay (f lip flop based) coarse delay adjustment range 0 17 ? clk in period 17 d elay s teps coar se delay resolution 169.54 ps f clkin = 2949.12 mhz maximum frequency coarse delay 1500 mhz clock output coarse delay (slip based) coarse dela y adjustment range 1 to clk in period resolution 339.08 ps f clkin = 2949.12 mhz maximum frequency coarse delay 1600 mhz 1 guaranteed b y design and characterization.
HMC7043 data sheet rev. b | page 6 of 43 clock output driver characteristics table 7 . parameter min typ max unit test conditions/comments cml mode (low power) r l = 100 ? , 9.6 ma ?3 db bandwidth 1950 mhz differential output voltage = 980 mv p - p diff output rise time 175 ps f clkout = 245.76 mhz, 20% to 80% 145 ps f clkout = 983.04 mhz, 20% to 80% output fall time 185 ps f clkout = 245.76 mhz, 20% to 80% 145 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 1390 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1360 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage v cc ? 1.05 v f clkout = 245.76 mhz (2949.12 mhz/12) cml mode (high power) r l = 100 ? , 14.5 ma ?3 db bandwidth 1 5 00 mhz d ifferential output voltage = 147 0 mv p - p diff output rise time 250 ps f clkout = 245.76 mhz, 20% to 80% 165 ps f clkout = 983.04 mhz, 20% to 80% output fall time 255 ps f clkout = 245.76 mhz, 20% to 80% 170 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 2000 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1800 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) differential output voltage magnitude 590 mv p - p diff f clkout = 3200 mhz power ? 3.6 dbm diff f clkout = 3200 mhz common - mode output voltage v cc ? 1.6 v f clkout = 245.76 mhz (2949.12 mhz/12) lvpecl mode r l = 150 ? , 4.8 ma ?3 db bandwidth 2400 mhz differential output voltage = 1240 mv p - p diff output rise time 135 ps f clkout = 245.76 mhz, 20% to 80% 130 ps f clkout = 983.04 mhz, 20% to 80% output fall time 135 ps f clkout = 245.76 mhz, 20% to 80% 130 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 1760 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1850 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) differential output voltage magnitude 930 mv p - p diff f clkout = 3200 mhz power 0.3 dbm diff f clkout = 3200 mhz common - mode output voltage v cc ? 1.3 v f clkout = 245.76 mhz (2949.12 mhz/12) lvds mode (low power) 1.75 ma maximum operating frequency 1700 mhz differential output voltage = 320 mv p - p diff output rise time 135 ps f clkout = 245.76 mhz, 20% to 80% 100 ps f clkout = 983.04 mhz, 20% to 80% output fall time 135 ps f clkout = 245.76 mhz, 20% to 80% 95 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 390 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) common - mode output voltage 1.1 v f clkout = 245.76 mhz (2949.12 mhz/12)
data sheet HMC7043 rev. b | page 7 of 43 parameter min typ max unit test conditions/comments lvds mode (high power) 3.5 ma maximum operating frequency 1700 mhz differential output voltage = 6 0 0 mv p - p diff output rise time 145 ps f clkout = 245.76 mhz, 20% to 80% 105 ps f clkout = 983.04 mhz, 20% to 80% output fall time 145 ps f clkout = 245.76 mhz, 20% to 80% 100 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 750 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 730 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage 1.1 v f clkout = 245.76 mhz (2949.12 mhz/12) cmos mode maximum operating frequency 600 mhz single - ended ou tput voltage = 940 mv p - p diff output rise time 425 ps f clkout = 245.76 mhz, 20% to 80% output fall time 420 ps f clkout = 245.76 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) output voltage high v cc v load current = 1 ma v cc ? 0.5 v load current = 10 ma low 0.07 v load current = 1 ma 0.5 v load current = 10 ma 1 guaranteed by design and characterization.
HMC7043 data sheet rev. b | page 8 of 43 absolute maximum rat ings table 8 . parameter rating vcc1, vcc2, vcc3, vcc4, vcc5, vcc6, vcc7 to ground ? 0.3 v to +3.6 v maximum junction temperature 125 c thermal resistance ( c hannel to g round p ad) 7 c/w storage temperature range ? 65c to + 125 c operating temperature range ? 40c to + 85 c peak reflow temperature 260c esd sensitivity level human body model (hbm) class 1c charged device model (cdm) 1 class 4 1 per jesd22 - c101 - f (cdm) standard. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions ab ove those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet HMC7043 rev. b | page 9 of 43 pin configuration and function descrip tions 1 2 3 sclkout9 sclkout9 gpio 4 sd at a 5 sclk 6 slen 7 vcc5_sysref 24 rsv 23 sclkout7 22 sclkout7 21 clkout6 20 clkout6 19 vcc3_out 18 clkout4 17 clkout4 16 sclkout5 15 sclkout5 14 rsv 13 vcc2_out 44 sclkout13 45 sclkout13 46 clkout12 47 clkout12 48 vcc7_out 43 sclkout 1 1 42 sclkout 1 1 41 clkout10 40 clkout10 39 vcc6_out 38 clkout8 37 clkout8 t o p view (not to scale) HMC7043 25 clkout2 26 clkout2 27 sclkout3 28 sclkout3 29 vcc1_clkdist 30 ldobyp2 31 bgapbyp1 32 reset 33 sclkout1 34 sclkout1 35 clkout0 36 clkout0 8 rfsyncin 9 rfsyncin 10 vcc4_clkin 1 1 clkin 12 clkin notes 1. rsv = rese r ved pin and must be tied t o ground. 2. connect the exposed pad to a high quality rf/dc ground. 13 1 14-002 figure 2. table 9 . pin function descriptions pin n o. mnemonic type 1 description 1 clk out0 o true clock output channel 0. default dclk profile. 2 clkout0 o complementary clock output channel 0. default dclk profile. 3 sclkout 1 o true clock output channel 1. default sysref profile. 4 sclkout1 o complementary clock output channel 1. default sysref profile. 5 reset i device reset input. active high. for normal operation, set reset to 0. 6 bgap byp 1 band gap bypass capacitor connection. connect a 4.7 f capacitor to ground. this pin affects all internally regulated supplies. 7 ldobyp2 ldo bypass 2. connect a 4.7 f capacitor to ground. the internal digital supply is 1.8 v. this pin is the ldo bypass for the sysref section. 8 vcc1_clkdist p 3.3 v supply for clk di stribution . 9 sclkout3 o true clock output channel 3. default sysref profile. 10 sclkout3 o complementary clock output channel 3. default sysref profile. 11 clkout2 o true clock output channel 2. default dclk profile. 12 clkout2 o complementary clock output channel 2. default dclk profile. 13 vcc2_out p power supply for clock group 1 (southwest) channel 2 and channel 3. see the clock grouping, skew , and crosstalk section. 14 rsv r reserved p in . this pin must be t ie d to ground. 15 sclkout5 o true clock output channel 5. default sysref profile. 16 sclkout5 o complementary clock output channel 5. default sysref profile. 17 clkout4 o true clock output channel 4. default dclk profile. 18 clkout4 o complementary clock output channel 4. default dclk profile. 19 vcc3_out p power supply for clock group 2 (south) channel 4, channel 5, channel 6, and channel 7. see the clock grouping, skew , and crosstalk section. 20 clkout6 o true clock output channel 6. default dclk profile. 21 clkout6 o complementary clock output channel 6. default dclk profile. 22 sclkout7 o true clock output channel 7. default sysref profile. 23 sclkout7 o complementary clock output channel 7. default sysref profile. 24 rsv r reserved pin. this pin must be t ie d to ground. 25 clkin i complementary clock input . 26 clkin i true clock input .
HMC7043 data sheet rev. b | page 10 of 43 pin n o. mnemonic type 1 description 27 vcc4_clkin p power s upply for the clock input path . 28 rfsyncin i true rf s ynchronization i nput with d eterministic d elay . 29 rfsyncin i complementary rf s ynchronization i nput with d eterministic d elay . 30 vcc5_sysref p power supply for common sysref divider. 31 slen i/o spi l atch e nable . 32 sclk i/o spi c lock . 33 sdata i/o spi d ata . 34 gpio i/o programmable g eneral -p urpose input/output . 35 sclkout9 o true clock output channel 9. default sysref profile. 36 sclkout9 o complementary clock o utput channel 9. default sysref profile. 37 clkout8 o true clock output channel 8. default dclk profile. 38 clkout8 o complementary clock o utput channel 8. default dclk profile. 39 vcc6_out p power supply for clock group 3 (north) channel 8, channel 9, channel 10, and channel 11. see the clock grouping, skew , and crosstalk section. 40 clkout10 o true clock output channel 10. default dclk profile. 41 clkout10 o complementary clock o utput channel 10. default dclk profile. 42 sclkout11 o true clock output channel 11. default sysref profile. 43 sclkout11 o complementary clock o utput channel 11. default sysref profile. 44 sclkout13 o true clock output channel 13. default sysref profile. 45 sclkout13 o complementary clock output channel 13. default sysref profile. 46 clkout12 o true clock output channel 12. default dclk profile. 47 clkout12 o complementary clock output channel 12. default dclk profile. 48 vcc7_out p power supply for clock group 0 (northwest) channel 0, channel 1, channel 12, and channel 13. see the clock grouping, skew , and crosstalk section. ep exposed pad. c onnect the exposed pad to a high quality rf/dc ground. 1 o is output, i is input, p is power, r is reserved, and i/o is input/output .
data sheet HMC7043 rev. b | page 11 of 43 typical performance characteristics ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 1 10 100 1000 10000 phase noise (dbc/hz) frequenc y offset (khz) hmc7044-clock source HMC7043 13 1 14-003 hmc7044 as clock source: output freq = 983.04mhz output power = 3.7dbm 1mhz, ?140.56dbc/hz 5mhz, ?153.26dbc/hz 10mhz, ?154.28dbc/hz 20mhz, ?154.85dbc/hz rms jitter (12khz t o 20mhz): 73.74fs HMC7043 outpu t : a t fundemen t a l mode 1mhz, ?140.30 dbc/hz 5mhz, ?151.02 dbc/hz 10mhz, ?151.77 dbc/hz 20mhz, ?151.97 dbc/hz rms jitter = 77.01fs figure 3 . additive j jitter at 983.04 mhz at o utput 13 1 14-004 ?170 ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 1 10 100 1000 10000 phase noise (dbc/hz) frequenc y offset (khz) hmc830-clock source HMC7043 hmc830 as clock source: output freq = 983.04mhz output power = 4dbm 1mhz, ?144.49dbc/hz 5mhz, ?158.38dbc/hz 10mhz,?162.61dbc/hz 20mhz, ?164.29dbc/hz HMC7043 outpu t : a t fundemen t al mode 1mhz, ?144.31 dbc/hz 5mhz, ?153.46 dbc/hz 10mhz, ?154.78 dbc/hz 20mhz, ?155.18 dbc/hz figure 4. absolute phase noise measured at 983.04 mhz at o utput 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100m 1g 3.2g differentia l output vo lt age (vp-p diff) frequenc y (hz) 13 1 14-206 l v p e c l c m l 100 h igh c m l 100 l o w l v d s high c m o s (not in differentia l mode) figure 5. differential output power vs. frequency over various modes 0 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.80 1.95 2.10 2.25 1.0 1.5 2.0 2.5 3.0 3.5 differential output voltage (v p-p) frequency (ghz) lvpecl cml100 high cml100 low lvds high 13114-100 figure 6. differential output voltage vs. frequency over various modes differentia l output vo lt age (vp-p diff) frequenc y (hz) 0 0.25 0.5 0.75 1.00 1.25 1.5 1.75 2.00 100m 1g 3g ?40c +25c +85c 13 1 14-205 figure 7. lvpecl different ial output power vs. frequency over various temperatures ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.4 0.8 1.2 1.6 2.0 clkout0/clkout0 vo lt age (v) time (ns) 13 1 14-007 figure 8. differential clkout0/ clkout0 at 2457 mhz, lvpecl
HMC7043 data sheet rev. b | page 12 of 43 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 6 7 8 9 10 time (ns) 13114-008 clkout0/clkout0 vo lt age (v) fig ure 9. differential clkout0/ clkout0 v oltage at 614.4 mhz, lvpecl 13 1 14-009 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 200 400 600 800 1000 clock grou p v alid phase alarm vo lt age (v) clock ouput vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm figure 10 . output channel synchronization before and after rephase 13 1 14-010 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 330 335 340 345 350 clock grou p v alid phase alarm vo lt age (v) clock output vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm figure 11 . output channel synchronization before rephase 13 1 14-0 1 1 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 695 700 705 710 715 clock grou p v alid phase alarm vo lt age (v) clock output vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm ?0.5 0 0.5 1.0 1.5 2.0 2.5 figure 12 . output channel synchronization after rephase 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 13 1 14-012 10 15 20 25 30 del a y ste p size (ps) del a y ste p ?40c + 25c + 85c figure 13 . analog delay step size vs. delay step over temperature , lvpecl at 983.04 mhz 13 1 14-013 ?200 ?100 0 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 del a y ste p size (ps) del a y ste p fund:fundamen t al mode a t 2949.12mhz dis: analog del a y is disabled a t 983.04mhz fund dis ?40c + 27c + 85c figure 14 . analog delay vs. delay set ting over temperature, lvpecl at 983.04 m hz
data sheet HMC7043 rev. b | page 13 of 43 typical application circuits 100? 0.1f 0.1f downstream device l vds output high impedance input HMC7043 13 1 14-014 figure 15 . ac - coupled lvds output driver 0.1f 0.1f downstream device cm l output high impedance input HMC7043 100? 100? vcc 100? 13 1 14-015 figure 16 . ac - coupled cml (configured high - z) output driver 0.1f 0.1f downstream device cm l output high impedance input HMC7043 100? 100? vcc 100? 13 1 14-016 figure 17 . ac - coupled cml (internal) output driver 0.1f 0.1f self biased re f , vcxo inputs HMC7043 13 1 14-017 figure 18 . clkin/ clkin , rfsyncin input differential mode 100? downstream device l vds output high impedance input HMC7043 13 1 14-018 figure 19 . dc - coupled lvds output driver downstream device ( l vpecl) l vpecl- com pa tible output HMC7043 50? 50? 50? gnd 13 1 14-019 figure 20 . dc - coupled lvpecl output driver cm l output HMC7043 100? 100? vcc downstream device (cml) 13 1 14-020 figure 21 . dc - coupled cml (internal) output driver 0.1f HMC7043 3.3v driver 0.1f 13 1 14-021 figure 22 . clkin, rfsyncin input single - ended mode
HMC7043 data sheet rev. b | page 14 of 43 terminology phase jitter and phase noise an ideal sine wave has a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is phase jitter. although many causes can contribut e to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. this phase jitter leads to the energy of the sine wave in the frequency domain spreading out , producing a continuous power spectrum. this power sp ectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). t he value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with res pect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 1 0 mhz ). this is the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of analog - to - digit al converters ( adcs ) , digital - to - analog converters ( dacs ) , and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a f requency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in b oth cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a samp ling clock for a dac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase nois e additive phase nois e is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any e xternal oscillators or clock sources is subtracted , which makes it possible to predict the degree to which the device impacts the total s ystem phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes a phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contrib utors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted , which makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contri butes a time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
data sheet HMC7043 rev. b | page 15 of 43 theory of operation the HMC7043 is a high performance, clock distribution ic designed for extending the number of clock signals across the system with minimal noise contribution. the device can be used for distributing t he noise sensitive reference clocks for high speed data converters with either parallel or serial (jesd204b) interfaces, fpgas , and local oscillators. the HMC7043 is designed to meet the require ments of demanding base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. the device provides 14 low noise and configurable outputs to offer flexibility in distrib uting clocks while applying frequency division, phase adjustment, cycle slip, and external signal synchronization options. the HMC7043 generates up to seven dclk and sysref clock pairs per the jesd204b interface requirements. the system designer can generate a lower number of dclk and sysref pairs, and configure the remaining output signal paths as dclks , additional sysrefs , or other reference clocks with independent phase and frequency adjustme nt. frequency adjustment can be accomplished by selecting the appropriate output divider values. one of the unique features of the HMC7043 is the independent flexible phase management of each o f the 14 channels. using a combination of divider slip based, digital ( coarse ) and analog ( fine ) delay adjustments, each channel can be programmed to have a different phase offset. the phase adjustment capability allows the designer to offset board flight time delay variations, match data converter sample window s , and meet jesd204b synchronization challenges. the output signal path design of the HMC7043 is implemented to ensure both linear phase adjustment steps and minimal noise perturbation when phase adjustment circuits are turned on. the HMC7043 provide s output clock signals of up to 3.2 ghz, while having the flexibility to support input reference frequencies of up to 6 ghz when the internal clock division blocks are turned on. the higher frequency support enables higher bandwidth rf designs, and allows for distribution of low noise rf pha se - locked loop ( pll ) voltage controlled oscillator ( vco ) outputs as well as other critical clocks across the system. one of the key challenges in jesd204b system design is ensuring t he synchronization of data converter frame alignment across the system, fr om the fpga or digital front end ( dfe ) to adcs a nd dacs through a large clock tree that may comprise multipl e clock generation and distribution ics. there are two input path s on the HMC7043 ; on e is for the clock signal that is distributed, and the other may be used as an external synchronization signal. in typical jesd204b systems , s erial data converter interfaces, there may be a need to ensure th at all clock signals that are sent to the data converters have phases which are controlled by an fpga . by virtue of the rf sync input, the device ensures that output signals have a deterministic phase alignment to this synchronization input. the rf sync input can also implement multiple device clock trees by nesting more than one HMC7043 to generate an even larger clock distribution network, while still maintaining phase alignment across the clock tree. offe ring excellent crosstalk, frequency isolation, and spurious performance, the device generates independent frequencies in both single - ended and differential formats including lvpecl, lvds, cml , and cmos , and different bias conditions to offset varying board insertion losses. the outputs can also be programmed for ac or dc coupling and 50 or 100 internal and external termination options. the HMC7043 is programmed via a 3 - wire serial port interface (spi). the HMC7043 is offered in a 48 - lead, 7 mm 7 mm, lfcsp package with the exposed pad to ground.
HMC7043 data sheet rev. b | page 16 of 43 detaile d b lock diagram sysref timer analog del a y clk distribution pa th clkout0 clkout0 sclkout1 sclkout1 mux mux sync/pulsor contro l t o leaf dividers coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) fundamen t al mode fundamen t al mode fundamen t al mode fundamen t al mode fundamen t al mode fundamen t al mode analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y clkout2 clkout2 sclkout3 sclkout3 clkout8 clkout8 sclkout9 sclkout9 mux mux coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y gpi spi mux mux analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) fundamen t al mode fundamen t al mode fundamen t al mode fundamen t al mode analog del a y clkout4 clkout4 sclkout5 sclkout5 clkout10 clkout10 sclkout 1 1 sclkout 1 1 mux mux coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y mux mux analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) fundamen t al mode fundamen t al mode fundamen t al mode fundamen t al mode ldos analog del a y clkout6 clkout6 sclkout7 sclkout7 clkout12 clkout12 sclkout13 sclkout13 mux mux coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y bgabyp1 ldobyp2 spi sdat a sclk slen alarm gener a tion device contro l reset gpio coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) analog del a y mux mux analog del a y coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) coarse digi t al del a y cycle slip/ sync divider (1 t o 4094) clkin clkin rfsyncin rfsyncin 13 1 14-022 divider 1, 2 figure 23 . detailed block diagram clock i nput n etwork input termination network common for all input buffers the two clock and rfsync i nput buffers share similar architecture and control features the input termination network is configurable to 100 , 200 , and 2 k differentially it is typically ac - coupled on the board, and uses the on - chip resistive divider to set the internal common - mode voltage, v cm , to 21 v by closing the 50 termination switch (see figure 24 ), the network also can serve as the termination system for an vpec driver although the input t ermination network for the two clock a nd rfsync input buffers is identical, the buffer behind the network is different 2.8v 4k? 5k? 50? 50?, 100?, 1k? 50?, 100?, 1k? 1pf 13033-045 figure 24 . on - chip termination network for c lock and rfsync bu ffers recommendations for normal use for both b uffer types , unless there are extenuating circumstance s in the application, us e 100 differential termina tion resistors to c ontrol reflections, to us e the on - chip dc bias network to set the common mode level, and to externally ac couple the input signals in d o not us e a receiver side dc termination of the vpec signal
data sheet HMC7043 rev. b | page 17 of 43 single - ended operation the buffers can support a single - ended signal with slightly reduced input sensitivity and b andw idth. if driving any of the buffers single - ended, ac couple the unuse d leg of the buffer to ground at the input of the die. maximum signal swing considerations the internal supplies to these input buffers are supplied directly from 3.3 v. the esd network and parasitic diodes can generally shunt away excess power and protect the internal circuits (withstanding reference powers above 13 dbm). nevertheless, to protect from latch - up concerns, the signals on the reference inputs must not exceed the 3.3 v internal supply. for a 2.1 v common mode, 50 single - ended source, this all ows ~1200 mv of amplitude, or 11 dbm maximum reference power. clock output network the HMC7043 is a high performance cl ock buffer, is appropriate for j esd204b data converters , and much of the uniqueness of a jesd204b clock generation chip relates to the array of output channels. in this device, the output network requirements include ? a large n umber of device clock (dclk) and synchronization ( sysref) channels ? very good phase noi se floor of the dclk channels th at can be connected to critical data converter sample clock inputs ? deterministic phase alignment between all output channels relative to one another ? fine phase control of synchronization channels with respect to the dclk cha nnel ? frequency coverage to satisfy typical clock rates in systems ? skew between sysref and dclk channels that is much less than a dclk period ? spur and crosstalk performance that does not impact system budgets the HMC7043 output network supports the following recom - mended features, which are sometimes critical in user applications: ? deterministic s ynchronization of the output channels with respect to an exte rnal sig nal (rfsync) , which a llows multichip synchronization and cl ean expansion to larger systems ? pulse generator behavior to temporarily generate a synchronizati on pulse stream at a user request ? the f lexibility to define unused jesd204b sysref and dclk c hannels for other purposes ? glitchless phase control of signals relative to each other ? 50% duty cycle clocks with odd division ratios ? multi mode output buffers with a variety of swings and termination options ? skew between all channels is much less than a dcl k period ? adjustable performance vs . power consumption for less sensitive clock channels clock ga ting sync/pulse gener a t or contro l digi t al del a y and retime divider leaf controller sync_fsm_s ta te sync request (from spi or gpi pin) pulse gener a t or request (from spi or gpi pin) output channe l 14 sysref timer reset rf sync clkin pa th sysref input network q d 13 1 14-023 figure 25 . clock output network simplified diagram
HMC7043 data sheet rev. b | page 18 of 43 each of the 14 output channels are logically identical. the only distinction between the s ys ref and dclk channels is in the spi configuration, and in how the y are use d. each channel contains independent dividers, phase adjustment, and analog delay circuits . this combination provides the ultimate flexibility, cleanly accommodating nonjesd204b devices in the system. in addition to the 14 output channel dividers, an internal sysref timer continually operates, and the synchronization of the output channel divid ers occurs deterministically with respect to this timer, which the user can re ph ased deterministically by the user thr o u gh gpi or spi or deterministically by using the rfsync in/ rfsyncin differential pins. the pulse generator functionality of the jesd204b standard involve s temporarily generating sysref output pulses, with appropriate phasing, to downstream devices. the centralized sysref timer and the associated sync/ pulse generator control manage the process of enabling the in tended sysref channels, phasing them, and then disabling them for signal integrity and power saving advantages. b asic output divider channel e ach of the 14 output channels are logically identical, and support divide ratios from 1 to 4094. the supported odd divide ratios (1, 3, or 5) have 50.0% duty cycle. t he only distinction between a sysref channel and a device clock channel is in the spi configuration and the typical usage of a given channel. for basic functionality and phase contro l, each output path co nsists of the following: ? divider generate s the logic signal of the appropriate frequency and phase ? digital p hase a djust adjust s the phase of each channel in increments of ? cl ock input cycles ? retimer a low noise flip flop t o retime the channel, removing any accumulated jitter ? analog f ine d elay provide s a number of ~25 ps delay steps ? selection m ux selects the fundamental, divider, analog delay, or an alternate path ? multi m ode o utput b uffer low noise lvds, cml, cmos, or lvpecl the digital phase adjuster and retimer launch on either clock phase of the clock input, depending on the digital phase adjust setpoint (coarse digital delay[4:0]). to support divider synchronization, arbitrary phase slips , and pulse generator modes, the following blocks are included : ? a clock gating stage pause s the clock for synchronization or slip operations ? a n output channel leaf (14) c ontroller that manages slip, synch ronization , and pulse generator s with info rmation from the sysref finite state machine (fsm ) each channel has an array of control signals. some of the controls are described in table 10 . syste m wide broadcast signals can be triggered from the spi or general - purpose input (gpi) p ort to issue a sync command (to align dividers to the system internal sysref timer ) , issue a pulse generator stream, ( temporarily exporting sysref signals to receivers), or to cause the dividers to slip a number of clock input cycles to adjust their phases . individual dividers can be made sensitive to these events by adjusting their slip enable, sync enable, and start - up mode[1:0] configuration, as described in table 11. when output buffers are configured in cmos mode and phase alignment is required among the outputs, additional multisl ip delays must be issued for channel 0, channel 3, channel 5, channel 6, channel 9, channel 10, and channel 13. the value of the delay must be as large as half of the selected divider ratio. note that this requirement of having additional multislip delays is not needed when the channels are use d in lvpecl, cml, or lvds mode. if a channe l is configured to behave as a pulse generator , to temporarily power up and power down according to the gpi and spi pulse generator commands ; additional controls define the behavior outside of the pulse generator chain (see table 12) . e ach divider has an additional phase offset register that adjust s the start phase or influence s the behavior of slip events sent via the spi (see table 13) . table 14 outlines the typical configuration combinations for a dclk channel relative to a sysref s ynchronization channel. note that other combinations are possible. synchronization of downstream devices can be managed manually, or by using the pulse generator functionality of the HMC7043 . se e the t ypical programming sequence section for more information about the differences between the two methods .
data sheet HMC7043 rev. b | page 19 of 43 table 10 . basic divider controls bit name description channel e nable channel enable. if set to 0, the channel is disabled. if set to 1, the channel can be enabled depending on the settings of the start - up mode[1:0], seven pairs of 14 - chann el outputs enable[6:0], and sleep mode bits . 12 - bit channel divider[11:0] divide ratio. 12- bit divide ratio, split across two words (msb and lsb). set to 0 if not using the channel divider (output mux selection[1:0] = 2 or 3) high performance mode high performance mode. adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of power. the performance advantage is about 1 db, and the current penalty depends on whether the divider is enabled. coarse digital delay[4:0] digital delay. adjusts the phase of the divider signal by up to 17 ? cycles of the clock input. this circuit is practically noiseless; however, note that a low amount of additional current is consumed. fine analog delay[4:0] analog delay. adjusts the dela y of the divider signal in increments of ~25 ps. set output mux selection[1:0] = 1 to expose this chann el. exposing this channe l c auses phase noise degradation of up to 12 db; therefore, do not use on noise sensitive dclk channels. output mux selection[1: 0] output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock. fundamental mode can be generated with the divider (12 - bit channel divider[11:0] = 1), or via output mux selection[1:0] = 10 and 12 - bit channel divider[11:0] = 0. because the divider path consumes power and degrades phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path that is divider - based. such skew can be compensated for with delay (digi tal and analog) on the divider - based path. force mute[1] force mute . if 1, and the channel enable is true (channel ena ble = 1) and force mute[0] = 0 , the sig nal just before the output buffer is asynchronously forced to logic 0. to see the effect of this, the output buffer must be enabled, which is dependent on the dynamic driver enable and start - up mode[1:0] controls. table 11 . channel features bit name description slip enable slip enable. a channel processes slip requests broadcast from the spi or gpi (or, if multislip enable = 1, initiated following a recognized sync or pulse generator startup). sync enable sync enable. a channel processes synchronization events broadcast from the spi or gpi or due to sync/rf sync (via the sysref fsm) to reset the phase. this signal can be safely toggled on and off to adjust sync sensitivity without risking the state of the divider. start - up mode[1:0] 00 = asynchronous (normal mode). the d ivider starts with uncontrolled phase. it is rephased by sync events if sync enable = 1. 11 = dynamic ( pulse generator mode). the d ivider monitors pulse generator events broadcast from the sysref controller. it is powered up just before a pulse generator chain, rephased at the start, and powered down after the pulse generator chain. t his mode is onl y supported for divide ratios > 31. table 12. pulse g enerator mode behavio r o ption s bit name description dynamic driver enable dynamic output buffer enable ( pulse generator mode only). 0 = the output buffer is simply enabled/disabled with the main channel enable. 1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power down outside pulse generator events. force mute[0] idle at logic 0 ( pulse generator mode only). 1 = if the buffer remains on outside of the pulse generator chain, drive to logic 0. 0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to approximately v cm .
HMC7043 data sheet rev. b | page 20 of 43 table 13 . multis lip configuration bit name description multislip e nable allow multislip. this bit d etermines whether the 12 - bit multislip digital delay[11:0] parameter is used for multislip operations. note that a multislip operation is automatically started following a sync or pulse generator initiation if multislip enable = 1. 12- bit multislip digital delay[11:0] multislip amount . if multislip enable = 1, any slip events (caused by gpi, spi, sync, or pulse generator events) repeat the number of times set by 12 - bit multislip digital delay[11:0] to adjust the phase by the multislip amount clock input cycles. a value of 0 is not supported if multislip enable = 1. note that phase slips are free from a noise and current perspective, that is, no additional power is needed and with no noise degradation, but they take some time to occur. each slip oper ation takes a number of nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. an alarm is available for the user to indicate when all phase operations are complete. table 14 . typical configuration combinations bit name dclk pulse g enerator sysref manual sysref non jesd204b 12- bit channel divider [11:0] small big big any start - up mode - bit normal pulse generator normal normal fine analog delay [4:0] off optional optional off coarse digital delay [4:0] optional optional optional optional slip enable optional optional optional optional multi slip enable optional off optional optional high performance mode optional off off optional sync enable on on on optional dynamic driver enable dont care on dont care dont care force mute[1:0] dont care on dont care dont care synchronization fsm/ pulse g enerator timing figure 25 show a block diagram of the interface of the sync/ pulse generator control to the divider cha nnels and the internal sysref timer the sysref timer counts in periods defined by sysref time r 110 , a 12- bit setting from the spi the sysref timer seuences the enable, reset, and startup, and disable s the downstream dividers in the event of sync or pulse generator reuests program the sysref timer count to a submultiple of the lowest output freuency in the clock network, and never faster than 4 mz to synchronize the divider channels , it is recommended, though not reuired, that the sysref timer 110 bits be set to a related freuency that is either a factor or multiple of other freuencies on the ic t he pulse generator is defi ned with respect to the periods of this sysref timer, not with respect to the output period this b ehavior of the pulse generator lea ds to a timing constraint that must be consid ered to prevent any runt pulses from affecting the pulse generator stream figure 27 shows the start - up behavior of an example divider that is configured as a pulse generator , with a period matching the internal sysref period the startup of the pulse stream occurs a fixed number of clock input cycles after the fsm transitions to the start phase d isabling the pulse generator stream whe re the logic path is forced to zero comes from a combinational path directly from the fsm because the divider has the option for nearly arbitrary phase adustment , the stop condition can arrive w hen the pulse stream is a ogic 1 and create a runt pulse for pha se offsets of zero to ( 50 8 ) clock input cycles, and at clock input freuencies gz, this condition is met naturally within the design for clock input freuencies gz, it is recommended to use digital delay or slip offsets to increase the natural phase offset and avoid the stress condition s t he situation is avoided by never applyin g phase offset more than ( 50 8 ) clock input cycles to a n output channel configured as a pulse generator
data sheet HMC7043 rev. b | page 21 of 43 clear reset rf_sync sync request pulse generator request wait startup pulse generator timeout? sync setup pulse generator setup notify channel fsm what type of event is coming done power dividers/sync blocks, pause blocks, reset latches remove latch reset, prepare to start clocks start clocks, with clean timing, small pipeline delay wait until the number of pulse generator cycles expires remove power 13114-125 figure 26. synchronization fsm flowchart fsm state startup divider channel fixed number of clock input cycles from state change to startup, and any intentional digital/analog offset if mute signal arrives quickly relative to signal train, no runt pulse pulse generator = 2 done fsm state startup divider channel if control is too late relative to signal train, there is a runt pulse pulse generator = 2 done 13114-126 figure 27. start-up behavior of an example divider configured as a pulse generator
HMC7043 data sheet rev. b | page 22 of 43 clock grouping, skew , and crosstalk although the output channels are logically independent, for physical reasons , they are f irst grouped into pairs , called c lock groups. each clock group shares a reference, an input buffer, and a sync retime flip flop originating from the clock distribution network. t he second level of grouping is according to the supply pin. cloc k g roup 1 ( c hannel 2 and channel 3) is on an independent suppl y, and the other supply pins are each responsible for two clock groups. as the output cha nnels are more tightly coupled ( by shar ing a clock group or by sharing a supply pin ) , the skew is minimized . however, the isolation between those channels suffers. table 15 s hows the clock groupin g by location , and table 16 show the typical skew and isolation that can b e exp ected and how it scales with distance between output channels. isolation improves as either the aggressor or the affected frequencies decrease . nevertheless, for particularly important clock channels where spurious tones must be minimized, carefully consid er their frequency and channel configurations to isolate continuously running frequencies onto different supply domains. channels configured as pulse generator s are normally not an issue, because they are disabled during normal operation. table 15. supply pin clock grouping by location supply pin location clock group channel vcc2 _out south w est 1 2 3 vcc3 _out south 2 4 5 3 6 7 vcc 6 _out north east 4 8 9 5 10 11 vcc 7 _out northwest 6 12 13 0 0 1 table 16. typical skew and isolation vs. distance distance typical skew ps 1 gh isolation, differential db distant supply group 20 90 to 100 closest n eighbor on d ifferent s upply g roup 15 70 shared supply 10 60 same clock group 10 45
data sheet HMC7043 rev. b | page 23 of 43 output buffer details northwest northeast south southwest vcc7_out vcc2_out clkout12 clkout12 vcc6_out vcc3_out reset bgapbyp1 ldobyp2 vcc1_ clkdist sclkout5 sclkout5 clkout4 clkout4 clkout6 clkout6 sclkout7 sclkout7 clkout0 clkout0 sclkout9 gpio spi vcc5_ sysref vcc4_ clkin sclkout9 rfsyncin rfsyncin clkin clkin sclkout1 sclkout1 clkout2 clkout2 sclkout3 sclkout3 sclkout13 sclkout13 sclkout 1 1 sclkout 1 1 clkout10 clkout10 clkout8 clkout8 13 1 14-026 figure 28 . clock grouping figure 28 shows the clock groups by supply pin location on the package. with appropriate supply pin bypassing, the spurious noise of the outputs is improved. table 15 describes how the supply pins of each of the 14 clock channels are connected within the seven clock groups. clock channels that are closest to each other have the best channel to channel skew performance, but they also have the lowest isolation from each other. select critical signals that require high isolation from each other from groups with distant supply pin locations. an example of the expected isolation and channel to channel skew perfo rmance of the HMC7043 a t 1 ghz is provided in table 16. sysref valid interrupt one of the challenges in a jesd204b system is to control and minimize the latency from the primary system controller ic, typically an asic or fpga, to the data converters. to estimate the correct amount of latency in the system, the designer must know the time required for a mast er clock generator like the HMC7043 to provide the correct output phases at each output channel after receiving the synchronization request. typically, a period of time is required on the device to implement the change requests on the outputs due to internal state machine cycles, data transfers , and any propagation delays. the sysref v alid interrupt is a function to notify the user that the correct output settings and phase relationships are esta blished, allowing the user to identify quick ly that the desired sysref and device clock states are presented at the outputs of t he HMC7043 . the user has the flexibility to assign the sysref valid interrupt to a gpo pin or to use a software flag, set via register 0x007d, bit 2, which the user may poll as necessary. the flag notifies the user when the system is configured and operating in the desired state , or conversely when it is not ready. t ypical programming s euence to initialize the HMC7043 to an operational state, use the following programming procedure: 1. connect the HMC7043 to the rated power supplies. no specific power supply sequencing is necessary. 2. release the hardware reset by switching from logic 1 to logic 0 when all supplies are stable. 3. load the configuration updates (provided by analog devices , inc. ) to specific registers ( s ee table 40). 4. program the sysref timer. set the divide ratio (a submultiple of the lower output channel frequency). set the pulse generator mode configuration, for example, selecting the level sensitiv ity option and the number of pulses desired. 5. program the output channels. set the output buffer modes (for example, lvpecl, cml, and lvds). set the divide ratio, channel start - up mode, coarse/analog delays, and performance modes. 6. e nsure the clock input signal are provided to clkin.
HMC7043 data sheet rev. b | page 24 of 43 7. issue a software restart to reset the system and initiate calibration. toggle the restart dividers/fsms bit to 1 and then back to 0. 8. send a sync request via the spi (set the reseed request bit) to align the divider phases and send any initial pulse generator stream. 9. wait six sysref period s (6 sysref time r[ 11:0] ) t o allow the outputs to phase appropriately (~3 s in typical configurations). 10. confirm that the o utputs have all reached their phases by checking that the clock outputs phases status bit = 1. 11. at this time, initialize any other devices in the system. configure the slave jesd204b devices in the system to operate with the sysref signal outputs from the HMC7043 . the sy sref channels from the HMC7043 can be on either asynchronously or dynamically, and may temporarily turn on for a pulse generator stream. 12. slave jesd204b devices in the system must be configured to monitor the input sysref signal exported from the HMC7043 . at this point , sysref channels from the HMC7043 can either be on asynchronously (running) or on dynamically ( temporarily turn on for a pulse generator train ) . 13. when all jesd204b slaves are powered and ready, send a pulse generator request to send out a pulse generator chain on any sysref channels programmed for pulse generator mode. the system is initialized. for power savings and the reduction of the cross coupling of frequencies on the HMC7043 , shut down the sysref channels. 1. program each jesd204b slave to ignore the sysref input channel. 2. on the HMC7043 , disable the individual channel enable bits of each sysre f channel. to resynchronize one or more of the jesd204b slaves, use the following procedure: 1. set the channel enable and sync enable bit of the sysref channel of interest. 2. to prevent an output channel from responding to a sync request, disable the sync enable mask of each channel so that it continues to run normally without a phase adjustment. 3. issue a reseed request to phase the sysref channel properly with respect to the dc lk. 4. enable the jesd204b slave sensitivity to the sysref channel. 5. if the sysref channel is in pulse generator mode, wait at least 20 sysref periods from step 3, and issue a pulse generator request. power supply conside rations the output buffers are suscept ible to supply with a certain extent. the output buffers are also susceptible to supply noise, but to a lesser extent. a noise tone of ?60 dbv at a 40 mhz offset results in a ?90 dbc tone at the output of the buffers in cml mode and ?85 dbc in lvpecl mode. this result is a relatively flat frequency response, and these numbers are measured differentially. phase noise/spurs caused by supply noise on the output buffers do not scale with output frequency. table 17 lists the supply network of the HMC7043 by pin, showing the r elevant functional b locks. three different usage profiles are defined for the network, not including the output channel supplies, which are accounted fo r separately. the values lis ted under profile 0 to profile 2 in table 17 and table 18 are the typical currents of that block or feature. if a number is not listed in a profile column, a typical profile does not exist for that b lock or feature, but the user can mix and match features outside of the profile list, and can determine what the power consumption is going to be given the current listings per feature.
data sheet HMC7043 rev. b | page 25 of 43 table 17 . supply network of th e HMC7043 by pin for vcc1_ clkdist, vcc4_ clkin , and vcc5_ sysref circuit block comment typical current (ma) profile 1 0 1 2 vcc1_clkdist regulator to 1.8 v, bypassed on ldobyp2 2 2 2 2 sysref timer 1 1 gpo driver in h igh speed mode 2 clock input distribution network minimum possible value 84 8 84 34 sync retiming network minimum possible value 3 8 subtotal for vcc1_clkdist 10 8 7 36 vcc4_clkin clkin/ clkin b uffer 1 6 1 6 16 clkin/ clkin p ath extra current for divide by 2 7 rfsyncin/ rfsyncin 4 r etimer 3 rfsyncin/ rfsyncin b uffer 9 subtotal or vcc4_clkin 0 16 1 6 vcc5_sysref sysref input network 11 11 sysref counter base 12 12 sysref counter, sync network 4 subtotal for vcc5_sysref 27 0 23 0 subtotal (without output paths) 10 1 26 52 1 profile 0 is s leep m ode ; profile 1 is p ower - u p d efaults , sy sref timer running and rfsync buffer is disabled ; profile 2 is only one clock output enabled , sysref timer is not running and rfsync buffer is disabled. 2 the c urrent is highly dependent on rat e of input/output and load of input/output traces. for heavily loaded traces, it i s recommended to use a series resistance of ~100 ? to minimize the ir drop on the internal regulator during transitions. 3 a temporary current o nly . 4 transient current in synchronization mode, can be temporarily enabled when using external synchronization.
HMC7043 data sheet rev. b | page 26 of 43 table 18. supply network of the HMC7043 by pin for the clock output network per output channel comment typical current (ma) profile 1 0 1 2 3 4 digital regulator and o ther s ources 2.5 0.5 2.5 2.5 2.5 2.5 buffer lvpecl including term currents 43 43 43 43 cml100 high power including term currents 31 low p ower 24 lvds high power at 307 mhz 10 10 low p ower 8 cmos at 100 mhz, both sections 25 channel mux included 2 different power modes deleted 2 2 2 2 digital delay off included 2 setpoint > 1 3 3 3 analog delay off included 2 0 min imum setting glitchless mode enabled 9 9 max imum setting 9 9 divider logic 0 not using divider path included 2 0 0 1 27 2 24 3 31 4 28 5 30 6 26 8 28 16 29 29 32 29 2044 29 29 sync logic 3 4 slip logic 3 4 subtotal 2.5 48 87 13 89 1 profile 0 is s leep m ode ; profile 1 is fundamental mode; profile 2 is sysref channel matched to fundamental mode ; profile 3 is lvds high power signal source from other channel ; and profile 4 is w orst case configuration for power consumption of a channel . 2 the base current consumption of the circuit (for example, mux) is included in the buffer typical current. 3 currents only occur temporarily during a synchronization event.
data sheet HMC7043 rev. b | page 27 of 43 s erial c ontrol p ort serial p ort i nterface (s pi ) c ontrol the HMC7043 can be controlled via the spi using 24 - bit registers and three pins: serial port enable (slen) serial data input/output (sdata) , and serial clock ( sclk). the 24 - bit register, shown in table 19 , consists of the following: ? 1 - bit read/write command ? 2 - bit multibyte field (w1, w0) ? 13- bit address field (a12 to a0) ? 8 - bit dat a fie ld (d7 to d0) table 19 . spi bit map msb lsb bit 23 bit 22 bit 21 bits[20:8] bits[7:0] r/w w1 w0 a12 to a0 d7 to d0 typical read cycle a typical read cycle is shown in figure 29 and occurs as follows : 1. the master (host) asserts both slen and sdata to indicate a read, followed by a rising edge sclk. the slave ( HMC7043 ) reads sdata on the first rising edge of sclk after slen. setting sdata high initiates a read. 2. the host places the 2 - bit multibyte field to be written to low (0) on the next two falling edges of sclk. the HMC7043 registers the 2 - bit multibyte field on the next two rising edges of sclk. 3. the host places the 13 - bit address field (a12 to a0) msb first on sdata on the next 13 falling edges of sclk. the HMC7043 registers the 13 - bit address field (msb first) on sdata over the next 13 rising edges of sclk. 4. the host registers the 8 - bit data on the next eight rising edges of sclk. the HMC7043 places 8 - bit data (d7 to d0) msb first on the next eight falling edges of sclk. 5. deassertion of slen completes the register read cycle. typical write cycle a typical write cycle is shown in figure 30 and occurs as follows : 1. the master (host) asserts both slen and sdata to indicate a read, followed by a rising edge sclk. the slave ( HMC7043 ) reads sdio on the first rising edge of sclk after slen. setting sdata low initiates a write. 2. the host places the 2 - bit multibyte field to be written to low (0) on the next two falling edg es of sclk. the HMC7043 registers the 2 - bit multibyte field on the next two rising edges of sclk. 3. the host places the13 - bit address field (a12 to a0), msb first , on sdata on the next 13 falling edges of sclk. the HMC7043 registers the 13 - bit address field (msb first) on sdio over the next 13 rising edges of sclk. 4. the host places the 8 - bit data (d7 to d0) msb first on the next eight fal ling edges of sclk. the HMC7043 register the 8 - bit data (d7 to d0) msb first on the next eight rising edges of sclk. 5. the final rising edge of sclk performs the internal data transfer into the re gister file, updating the configuration of the device. 6. deassertion of slen completes the register write cycle. sclk 1 x read w1 w0 a12 a 1 1 a0 d7 d6 d0 2 3 4 5 16 17 18 24 sd at a slen 13 1 14-128 figure 29 . spi timing diagram, read operation sclk 1 x write w1 w0 a12 a 1 1 a0 d7 d6 d0 2 3 4 5 16 17 18 24 sd at a slen 13 1 14-129 figure 30 . spi timing diagram, write operation
HMC7043 data sheet rev. b | page 28 of 43 control r egisters control register map table 20 . control register map address (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) global control 0x0000 global soft reset control reserved soft reset 0x00 0x0001 global request and mode control reseed request high performance distribution path reserved reserved mute output drivers pulse generator request restart dividers/ fsms sleep mode 0x00 0x0002 reserved multislip request reserved 0x00 0x0003 global enable control reserved rf reseeder enable reserved sysref timer enable reserved reserved 0x34 0x0004 reserved seven pairs of 14 - channel outputs enable[6:0] 0x7f 0x0005 global mode and enable control reserved 0x0f 0x0006 global clear alarms reserved clear alarms 0x00 0x0007 global miscellaneous control reserved 0x00 0x0008 reserved (scratchpad) 0x00 0x0009 reserved 0x00 input buffer 0x000a clkin0/ clkin0 input buffer control reserved input buffer mode[3:0] buffer enable 0x07 0x000b clkin1/ clkin1 input buffer control reserved input buffer mode[3:0] buffer enable 0x07 gpio/sdata control 0x0046 gpi control reserved gpi selection [2:0] gpi enable 0x00 0x0050 gpo control reserved gpo selection[ 4 :0] gpo mode gpo enable 0x37 0x0054 sdata control reserved sdata mode sdata enable 0x03 sysref/sync 0x005a pulse generator control reserved pulse g enerator mode selection[2:0] 0x00 0x005b sync control reserved sync retime reserved sync invert polarity 0x04 0x005c sysref timer control sysref timer[7:0] (lsb) 0x00 0x005d reserved sysref timer[11:8] (msb) 0x01 clock distribution network 0x0064 clock i nput c ontrol reserved divide by 2 on clock input low frequency clock input 0x00 0x0065 analog delay common control reserved analog delay low power mode 0x00 alarm masks register 0x0071 alarm mask control reserved sync request mask reserved clock outputs phase status mask sysref sync status mask reserved 0x10 product id registers 0x0078 product id product id value[7:0] (lsb) 0x0079 product id value[15:8] (mid) 0x007a product id value[23:16] (msb)
data sheet HMC7043 rev. b | page 29 of 43 address (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) alarm readback status registers 0x007b readback register reserved alarm signal 0x007d alarm readback reserved sync request status reserved clock outputs phases status sysref sync status reserved 0x007f alarm readback reserved sysref status register 0x0091 sysref status register reserved channel outputs fsm busy sysref fsm state[3:0] 0x00 other controls 0x0098 reserved reserved 0x00 0x0099 reserved reserved 0x00 0x009d reserved reserved 0xaa 0x009e reserved reserved 0xaa 0x009f reserved reserved 0x55 0x00a0 reserved reserved 0x56 0x00a2 reserved reserved 0x03 0x00a3 reserved reserved 0x00 0x00a4 reserved reserved 0x00 0x00ad reserved reserved 0x00 0x00b5 reserved reserved 0x00 0x00b6 reserved reserved 0x00 0x00b7 reserved reserved 0x00 0x00b8 reserved reserved 0x00 clock distribution 0x00c8 channel output 0 control high performance mode sync enable slip enable reserved start - up m ode[1:0] multislip enable channel enable 0xf3 0x00c9 12- bit channel divider[7:0] (lsb) 0x04 0x00ca reserved 12- bit channel divider[11:8] (msb) 0x00 0x00cb reserved fine analog delay[4:0] 0x00 0x00cc reserved coarse digital delay[4:0] 0x00 0x00cd 12- bit multislip digital delay[7:0] (lsb) 0x00 0x00ce reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x00cf reserved output mux selection[1:0] 0x00 0x00d0 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x00d2 channel output 1 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x00d3 12- bit channel divider[7:0] (lsb) 0x00 0x00d4 reserved 12- bit channel divider[11:8] (msb) 0x01 0x00d5 reserved fine analog delay[4:0] 0x00 0x00d6 reserved coarse digital delay[4:0] 0x00 0x00d7 12- bit multislip digital delay[7:0] (lsb) 0x00 0x00d8 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x00d9 reserved output mux selection[1:0] 0x00 0x00da idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30
HMC7043 data sheet rev. b | page 30 of 43 address (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 0x00dc channel output 2 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x00dd 12- bit channel divider[7:0] (lsb) 0x08 0x00de reserved 12- bit channel divider[11:8] (msb) 0x00 0x00df reserved fine analog delay[4:0] 0x00 0x00e0 reserved coarse digital delay[4:0] 0x0 0x00e1 12- bit multislip digital delay[7:0] (lsb) 0x00 0x00e2 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x00e3 reserved output mux selection[1:0] 0x00 0x00e4 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x00e6 channel output 3 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x00e7 12- bit channel divider[7:0] (lsb) 0x00 0x00e8 reserved 12- bit channel divider[11:8] (msb) 0x01 0x00e9 reserved fine analog delay[4:0] 0x00 0x00ea reserved coarse digital delay[4:0] 0x00 0x00eb 12- bit multislip digital delay[7:0] (lsb) 0x00 0x00ec reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x00ed reserved output mux selection[1:0] 0x00 0x00ee idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30 0x00f0 channel output 4 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x00f1 12- bit channel divider[7:0] (lsb) 0x02 0x00f2 reserved 12- bit channel divider[11:8] (msb) 0x00 0x00f3 reserved fine analog delay[4:0] 0x00 0x00f4 reserved coarse digital delay[4:0] 0x00 0x00f5 12- bit multislip digital delay[7:0] (lsb) 0x00 0x00f6 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x00f7 reserved output mux selection[1:0] 0x00 0x00f8 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x00fa channel output 5 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x00fb 12- bit channel divider[7:0] (lsb) 0x00 0x00fc reserved 12 - bit channel divider[11:8] (msb) 0x01 0x00fd reserved fine analog delay[4:0] 0x00 0x00fe reserved coarse digital delay[4:0] 0x00 0x00ff 12- bit multislip digital delay[7:0] (lsb) 0x00 0x0100 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0101 reserved output mux selection[1:0] 0x00 0x0102 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30
data sheet HMC7043 rev. b | page 31 of 43 address (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 0x0104 channel output 6 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x0105 12- bit channel divider[7:0] (lsb) 0x02 0x0106 reserved 12- bit channel divider[11:8] (msb) 0x00 0x0107 reserved fine analog delay[4:0] 0x00 0x0108 reserved coarse digital delay[4:0] 0x00 0x0109 12- bit multislip digital delay[7:0] (lsb) 0x00 0x010a reserved 12- b it multislip digital delay[11:8] (msb) 0x00 0x010b reserved output mux selection[1:0] 0x00 0x010c idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x010e channel output 7 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x010f 12- bit channel divider[7:0] (lsb) 0x00 0x0110 reserved 12- bit channel divider[11:8] (msb) 0x01 0x0111 reserved fine analog delay[4:0] 0x00 0x0112 reserved coarse digital delay[4:0] 0x00 0x0113 12- bit multislip digital delay[7:0] (lsb) 0x00 0x0114 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0115 reserved output mux selection[1:0] 0x00 0x0116 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30 0x0118 channel output 8 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x0119 12- bit channel divider[7:0] (lsb) 0x02 0x011a reserved 12- bit channel divider[11:8] (msb) 0x00 0x011b reserved fine analog delay[4:0] 0x00 0x011c reserved coarse digital delay[4:0] 0x00 0x011d 12- bit multislip digital delay[7:0] (lsb) 0x00 0x011e reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x011f reserved output mux selection[1:0] 0x00 0x0120 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x0122 channel output 9 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x0123 12- bit channel divider[7:0] (lsb) 0x00 0x0124 reserved 12 - bit channel divider[11:8] (msb) 0x01 0x0125 reserved fine analog delay[4:0] 0x00 0x0126 reserved coarse digital delay[4:0] 0x00 0x0127 12- bit multislip digital delay[7:0] (lsb) 0x00 0x0128 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0129 reserved output mux selection[1:0] 0x00 0x012a idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30
HMC7043 data sheet rev. b | page 32 of 43 address (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 0x012c channel output 10 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x012d 12- bit channel divider[7:0] (lsb) 0x02 0x012e reserved 12- b it c hannel d ivider[11:8] (msb) 0x00 0x012f reserved fine analog delay[4:0] 0x00 0x0130 reserved coarse digital delay[4:0] 0x00 0x0131 12- bit multislip digital delay[7:0] (lsb) 0x00 0x0132 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0133 reserved output m ux s election[1:0] 0x00 0x0134 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x0136 channel output 11 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xfd 0x0137 12- bit channel divider[7:0] (lsb) 0x00 0x0138 reserved 12- bit channel divider[11:8] (msb) 0x01 0x0139 reserved fine analog delay[4:0] 0x00 0x013a reserved coarse digital delay[4:0] 0x00 0x013b 12- bit multislip digital delay[7:0] (lsb) 0x00 0x013c reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x013d reserved output m ux s election[1:0] 0x00 0x013e idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30 0x0140 channel output 12 control high performance mode sync enable slip enable reserved start - up mode[1:0] multislip enable channel enable 0xf3 0x0141 12- bit channel divider[7:0] (lsb) 0x10 0x0142 reserved 12- bit channel divider[11:8] (msb) 0x00 0x0143 reserved fine analog delay[4:0] 0x00 0x0144 reserved coarse digital delay[4:0] 0x00 0x0145 12- bit multi - slip digital delay[7:0] (lsb) 0x00 0x0146 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0147 reserved output mux selection[1:0] 0x00 0x0148 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x01 0x014a channel output 13 control high performance mode sync enable slip enable reserved start - up mode [1:0] multislip enable channel enable 0xfd 0x014b 12- bit channel divider[7:0] (lsb) 0x00 0x014c reserved 12 - bit channel divider[11:8] (msb) 0x01 0x014d reserved fine analog delay[4:0] 0x00 0x014e reserved coarse digital delay[4:0] 0x00 0x014f 12- bit multislip digital delay[7:0] (lsb) 0x00 0x0150 reserved 12- bit multislip digital delay[11:8] (msb) 0x00 0x0151 reserved output mux selection[1:0] 0x00 0x0152 idle at zero[1:0] dynamic driver enable driver mode[1:0] reserved driver impedance[1:0] 0x30
data sheet HMC7043 rev. b | page 33 of 43 control register map bit descriptions global control (register 0x0000 to register 0x0009) table 21. global soft reset control address bits bit name settings description access 0x0000 [7:1] reserved reserved rw 0 soft reset resets all registers, divid ers, and fsms to default values table 22 . global request and mode control address bits bit name settings description access 0x0001 7 reseed request requests the centralized resync timer and fsm to reseed any of the output dividers that are programmed to pay attention to sync events. this signal is rising edge sensitive, and is only acknowledged if the resync fsm has completed all events (has finished any previous pulse generator and/or sync events, and is in the done state ( sysref fsm state[3:0] = 0010). rw 6 high performance distribution path high performance distribution path select. the clock distribution path has two modes. 0 power priority. 1 noise priority. provides the option for better noise floors on the divided output signals. 5 reserved reserved . 4 reserved reserved . 3 mute output drivers mutes the output drivers (dividers still run in the background). 2 pulse generator request asks for a pulse stream (see the t ypical programming sequence section). 1 restart dividers/fsms resets all dividers and fsms. does not affect configuration registers. 0 sleep mode forces shutdown. o utput network, and i/o buffers are disabled. 0x0002 [7: 2 ] reserved reserved. rw 1 multislip request requests a slip or multislip event from all divider channels that are sensitive to slip or multislip commands. the dividers are rising edge sensitive and take some time to process the request, after which the phase synchronization alarm is asserted. 0 reserved reserved. table 23 . global enable control address bits bit name settings description access 0x0003 [7:6] reserved reserved rw 5 rf reseeder enable enable rf reseed for sysref [4:3] reserved reserved 2 sysref timer enable enable internal sysref time reference 1 reserved reserved 0 reserved reserved 0x0004 7 reserved reserved rw [6:0] seven pairs of 14 - channel outputs enable[6:0] [0] enable channel 0 and 1 [1] enable channel 2 and 3 [2] enable channel 4 and 5 [3] enable channel 6 and 7 [4] enable channel 8 and 9 [5] enable channel 10 and 11 [6] enable channel 12 and 13 table 24 . global mode and enable control address bits bit name settings description access 0x0005 [7:0 ] reserved reserved rw
HMC7043 data sheet rev. b | page 34 of 43 table 25. global clear alarms address bits bit name settings description access 0x0006 [7:1] reserved reserved rw 0 clear alarms clear latched alarms table 26 . global miscellaneous control address bits bit name settings description access 0x0007 [7:0] reserved reserved. rw 0x0008 [7:0] reserved ( s cratchpad) reserved. the user can write/read to this registe r to confirm input/output s to the HMC7043 . this register does not affect device operation. rw 0x0009 [7: 0 ] reserved reserved. rw input buffer (register 0x000a to register 0x00 0b ) table 27 . clkin / clkin and rfsyncin / rfsyncin input buffer control address bits bit name settings description access 0x000a, 0x000b [7:5] reserved reserved rw [4:1] input buffer mode[3:0] input buffer control [ 0 ] enable internal 100 ? termination [ 1 ] enable ac coupling input mode [ 2 ] enable lvpecl input mode [ 3 ] high - z input enable 0 buffer enable enable input buffer gpio/sdata control (register 0x0046 to register 0x0054) table 28 . gpi control address bits bit name settings description access 0x0046 [7:4] reserved reserved rw [3:1] gpi selection[2:0] select the gpi fun ctionality, bits[2:0] 0000 select the gpi fu nctionality, bits[ 2 :0] 0001 reserved 0010 put the chip into sleep mode 0011 issue a mute 0100 issue a pulse generator request 0101 issue a reseed request 0110 issue a restart request 0111 reserved 1000 issue a slip request 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved. 1110 reserved 1111 reserved. 0 gpi enable gpi function enable. before changing the function of the pin, disable it first, and then reenable it after the function change. 1 1 note that it is possible to have a gpio delete pin configured as both an outp ut and an input.
data sheet HMC7043 rev. b | page 35 of 43 table 29 . gpo control address bits bit name settings description access 0x0050 7 reserved reserved rw [6:2] gpo selection[ 4 :0] select the gpo functionality, bits[ 4 :0] 00000 alarm signal 00001 sdata from spi communication 00010 sysref sync status has not synchronized since reset 00011 clock outputs phase status 00100 sync request status signal 00101 channel outputs fsm busy 00110 sysref fsm state 0 00111 sysref fsm state 1 01000 sysref fsm state 2 01001 sysref fsm state 3 01010 force logic 1 to gpo 01011 force logic 0 to gpo 01100 reserved 01101 reserved 01110 reserved 01111 reserved 10000 reserved 10001 reserved 10010 reserved 10011 reserved 10100 reserved 10101 reserved 10110 reserved 10111 reserved 11000 reserved 11001 pulse generator request status signal 11010 reserved 11011 reserved 11100 reserved 11101 reserved 11110 reserved 11111 reserved 1 gpo mode selects the mode of gpo driver 0 open - drain mode 1 cmos mode 0 gpo enable gpo driver enable table 30 . sdata control address bits bit name settings description access 0x0054 [7:2] reserved reserved rw 1 sdata mode selects the mode of sdata driver 0 open - drain mode 1 cmos mode 0 sdata enable sdata driver enable
HMC7043 data sheet rev. b | page 36 of 43 sysref/sync (register 0x005a to register 0 x005 d ) table 31. pulse g enerator c ontrol address bits bit name settings description access 0x005a [7:3] reserved reserved . rw [2:0] pulse g enerator mode selection[2:0] sysref o utput e nable with pulse generator. 000 level sensitive. when the gpi is configured to issue a pulse generator requ est (gpi selection[ 2 :0] = 100), or a pulse generator request is issued through the spi or as a sync p in - based pulse generator , run the pulse generator . otherwise, stop the pulse generator . 001 1 pulse . 010 2 pulses . 011 4 pulses . 100 8 pulses . 101 16 pulses . 110 1 6 pulse s . 111 continuous mode (50% duty cycle) . table 32 . sync control address bits bit name settings description access 0x005b [7:3] reserved reserved rw 2 sync retime 0 bypass the retime (non - deterministic sync event condition) 1 retime the external sy nc (deterministic sync event condition) 1 reserved reserved 0 sync polarity sync polarity (must be 0 if not using clkin/ clkin as the input) 0 positive 1 negative table 33 . sysref timer control address bits bit name settings description access 0x005c [7:0] sysref timer[7:0] (lsb) 12-b it sysref t imer setpoint lsb. this sets the internal beat frequency of the master timer, which controls synchronization and pulse generator events. set the 12 - bit timer to a submultiple of the lowest output sysref frequency, and program it to be no faster than 4 mhz. rw 0x005d [7:4] reserved reserved. rw [3:0] sysref timer[11:8] (msb) 12- bit sysref t imer setpoint msb. clock distribution network (register 0x0064 to register 0x0065) table 34 . cloc k input control address bits bit name settings description access 0x0064 [7:2] reserved reserved rw 1 divide by 2 on clock input use divide by 2 on clock input path 0 low frequency clock input changes bias to class a for low frequency clock input table 35 . analog delay common control address bits bit name settings description access 0x0065 [7:1] reserved reserved . rw 0 analog delay low power mode analog delay is low power mode. can save power for low settings of analog delay, but is not glitchless between setpoints.
data sheet HMC7043 rev. b | page 37 of 43 alarm masks register (register 0x0071) table 36 . alarm mask control register address bits bit name settings description access 0x0071 [7:5] reserved reserved rw 4 sync r equest m ask if set , a llow s ync r equest signals to generate an alarm signal 3 reserved reserved 2 clock o utputs p hase s tatus m ask if set, a llow c lock o utput p hases s tatus signal to generate an alarm signal 1 sysref s ync s tatus m ask if set, a llow sysref s ync s tatus signal to generate an alarm signal 0 reserved reserved product id registers (register 0x0078 to 0x007a) table 37 . product id registers address bits bit name settings description access 0x0078 [7:0] product id value[7:0] (lsb) 24-b it p roduct id value low r 0x0079 [7:0] product id value[15:8] (mid) 24 - b it p roduct id value mid r 0x007a [7:0] product id value[23:16] (msb) 24-b it p roduct id value high r alarm readback status registers (register 0x007b to 0x007f) table 38 . alarm readback status registers address bits bit name settings description access 0x007b [7:1] reserved reserved . r 0 alarm signal readback alarm status from spi . 0x007d [7:5] reserved reserved . r 4 sync request status u nsynchronized . 3 reserved reserved . 2 clock outputs phases status sysref alarm . 0 sysref of the HMC7043 is not valid; that is, the phase output is not stable. 1 sysref of the HMC7043 is valid; that is, the phase output is stable. 1 sysref sync status sysref sync status alarm . 0 the HMC7043 has been synchronized with an external sync pulse or a sync request from the spi. 1 the HMC7043 never synchronized with an external sync pulse or a sync request from the spi. 0 reserved 1 reserved . 0x007f [7:0] reserved reserved . r
HMC7043 data sheet rev. b | page 38 of 43 sysref status register (register 0x0091) table 39 . sysref status address bits bit name settings description access 0x0091 [7:5] reserved reserved . r 4 channel o utputs fsm b usy one of clock outputs fsm requested clock, and it is running . [3:0] sysref fsm state[3:0] indicates the current step of the sysref reseed process. note that the three different progressions are caused by different trigger events (reseed, pulse generator , reserved) . 0000 reset . 0010 done . 0100 get ready . 0101 get ready . 0110 get ready . 1010 running ( pulse generator ) . 1011 start . 1100 power up . 1101 power up . 1110 power up . 1111 clear reset . bias settings (register 0x0096 to register 0x00b8) for optimum performance of the chip, register 0x0098 to register 0x00b8 must be programmed to a different value than their default value table 40 . reserved registers address bits bit name settings description access 0x0098 [7:0] reserved reserved rw 0x0099 [7:0] reserved reserved rw 0x009d [7:0] reserved reserved rw 0x009e [7:0] reserved reserved rw 0x009f [7:0] reserved clock output driver low power setting (set to 0x4d instead of default value) rw 0x00a0 [7:0] reserved clock output driver high power setting (set to 0xd f instead of default value) rw 0x00a2 [7:0] reserved reserved rw 0x00a3 [7:0] reserved reserved rw 0x00a4 [7:0] reserved reserved rw 0x00ad [7:0] reserved reserved rw 0x00b5 [7:0] reserved reserved rw 0x00b6 [7:0] reserved reserved rw 0x00b7 [7:0] reserved reserved rw 0x00b8 [7:0] reserved reserved rw
data sheet HMC7043 rev. b | page 39 of 43 clock distribution (register 0x00c8 to regist er 0x015 2 ) the bit descriptions in table 41 apply to all 14 channels. table 41 . channel 0 to channel 13 control address bits bit name settings 1 description access 0x00c8, 0x00d2, 0x00dc, 0x00e6, 0x00f0, 0x00fa , 0x0104, 0x010e, 0x0118, 0x0122, 0x012c, 0x0136, 0x0140, 0x014a 7 high performance mode high performance mode. adjusts the divider and buffer bias to improve swing/phase noise at the expense of power. rw 6 sync enable susceptible to sync event. the c hannel can process a sync event to rese t the phase. 5 slip enable susceptible to slip event. the c hannel can process a slip request from spi or gpi. note that if slip enable is true, but multislip is off, a channel slips by 1 clock input cycle on an explicit slip request broadcast from the spi/gpi. 4 reserved reserved. [3:2] start - up mode[1:0] configures the channel to normal mode with asynchronous startup, or to a pulse generator mode with dynamic start - up. note that this must be set to asynchronous mode if the channel is unused. 00 asynchronous. 01 reserved. 10 reserved. 11 dynamic. 1 multislip enable allow multislip operation (default = 0 for sysref, 1 for dclk). 0 do not engage automatic multislip on channel startup. 1 multislip events after sync or pulse generator request, if the s lip enable b it = 1. 0 channel enable channel enable. if this bit is 0, channel is disabled. 0x00c9, 0x00d3, 0x00dd, 0x00e7, 0x00f1, 0x00fb, 0x0105, 0x010f, 0x0119, 0x0123, 0x012d, 0x0137, 0x0141, 0x014b [7:0] 12- bit channel divider[7:0] (lsb) 12- bit channel divider setpoint lsb. the divider supports even divide ratios from 2 to 4094. the supported odd divide r atios are 1, 3, and 5. all even and odd divide ratios have 50.0% duty cycle. rw 0x00ca, 0x00d4, 0x00de, 0x00e8, 0x00f2, 0x00fc, 0x0106, 0x0110, 0x011a, 0x0124, 0x012e, 0x0138, 0x0142, 0x014c [7:4] reserved reserved. rw [3:0] 12- bit channel divider[11:8] (msb) 12- bit channel divider setpoint msb . 0x00cb, 0x00d5, 0x00df, 0x00e9, 0x00f3, 0x00fd, 0x0107, 0x0111, 0x011b, 0x0125, 0x012f, 0x0139, 0x0143, 0x014d [7:5] reserved reserved. rw [4:0] fine analog delay[4:0] 24 fine delay steps. step size = 25 ps. values bigger than 23 has no effect on analog delay. 0x00cc, 0x00d6, 0x00e0, 0x00ea, 0x00f4, 0x00fe, 0x0108, 0x0112, 0x011c, 0x0126, 0x0130, 0x013a, 0x0144, 0x014e [7:5] reserved reserved. rw [4:0] coarse digital delay[4:0] 17 coarse delay steps. step size = ? input clock cycle. this flip flop (ff) - based digital delay does not increase noise level at the expense of power. values bigger than 17 ha ve no effect on coarse delay. 0x00cd, 0x00d7, 0x00e1, 0x00eb, 0x00f5, 0x00ff, 0x0109, 0x0113, 0x011d, 0x0127, 0x0131, 0x013b, 0x0145, 0x014f [7:0] 12- bit multislip digital delay[7:0] (lsb) 12- bit multislip digital delay amount lsb. step size = (delay amount: msb + lsb) input clock cycles. if multislip enable bit = 1, any slip eve nts (caused by gpi, spi, sync, or pulse generator events) repeat the number of times set by 12 -b it multislip digital delay[11:0] to adjust the phase by step size. rw
HMC7043 data sheet rev. b | page 40 of 43 address bits bit name settings 1 description access 0x00ce, 0x00d8, 0x00e2, 0x00ec, 0x00f6, 0x0100, 0x010a, 0x0114, 0x011e, 0x0128, 0x0132, 0x013c, 0x0146, 0x0150 [7:4] reserved reserved. rw [3:0] 12 - bit multislip digital delay[11:8] (msb) 12 - bit multislip digital delay amount msb . 0x00cf, 0x00d9, 0x00e3, 0x00ed, 0x00f7, 0x0101, 0x010b, 0x0115, 0x011f, 0x0129, 0x0133, 0x013d, 0x0147, 0x0151 [7:2] reserved reserved. rw [1:0] output mux selection[1:0] channel output mux selection. 00 channel divider output . 01 analog delay output . 10 other channel of the clock group pair. 11 input clock (fundamental). fundamental can also be generated with 12 - bit channel divider ratio = 1. 0x00d0, 0x00da, 0x00e4, 0x00ee, 0x00f8, 0x0102, 0x010c, 0x0116, 0x0120, 0x012a, 0x0134, 0x013e, 0x0148, 0x0152 [7:6] idle at zero[1:0] idle at logic 0 selection ( pulse generator mode only). force to logic 0 or vcm. rw 00 normal mode (selection for dclk) . 01 reserved. 10 force to logic 0. 11 force outputs to float, goes naturally to vcm. 5 dynamic driver enable dynamic driver enable ( pulse generator mode only). 0 driver is enabled/disabled with channel enable bit . 1 driver is dynamically disabled with pulse generator events. [4:3] driver mode[1:0] output driver mode selection. 00 cml mode . 01 lvpecl mode . 10 lvds mode . 11 cmos mode . 2 reserved reserved . [1:0] driver impedance[1:0] output driver impedance selection for cml mode. 00 internal resistor disable . 01 internal 100 ? resistor enable per output pin . 10 reserved . 11 internal 50 ? resistor enable per output pin . 1 x means dont care.
data sheet HMC7043 rev. b | page 41 of 43 a pplication s information evaluation pcb and schematic for t he circuit board in this application , use rf circuit design techniques. ensure that s ignal lines have 50 ? impedance . connect the package ground leads and exposed paddle directly to the ground pla ne similar to that shown in figure 32 and figure 33 . use a suffic ient number of via holes to connect the top and bottom ground planes. the evaluation circuit board is available from analog devices, inc., upon request. t he t ypical pb - free reflow solder profile shown in figure 31 is based on jedec j - std - 20c. 13 1 14-031 temper a ture (c) 217c ram p u p 3c/second max ram p down 6c/second max time (second) 60 t o 150 seconds 60 t o 180 seconds 20 t o 40 seconds 480 seconds max 260 ? 5/0c 150c t o 200c figure 31 . pb - free reflow solder profile 13 1 14-029 figure 32 . evaluation pcb layout, top side
HMC7043 data sheet rev. b | page 42 of 43 13 1 14-030 figure 33 . evaluation pcb layout, bottom side
data sheet HMC7043 rev. b | page 43 of 43 outline dimensions 1 1-20-2015-b 0.50 bsc bottom view top view pin 1 indic a t or exposed pad pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref 5.50 ref coplanarity 0.08 0.31 0.25 0.19 7.10 7.00 sq 6.90 0.90 0.85 0.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min 5.66 5.60 sq 5.54 48 1 13 12 24 25 36 37 pkg-000000 figure 34 . 48 - lead lead frame chip scale package [lfcsp] 7 mm 7 mm body and 0.85 mm package height (hcp - 48 - 1) dimensions shown in millimeters 12-10-2015- a notes: 1. 10 sprocket hole pitch cumul a tive t olerance 0.20 2. camber in compliance with ei a 481 3. m a terial: conductive black po l ystyrene 4. measured on a plane 0.30 mm above the bot t om of the pocket 5. measured from a plane on the inside bot t om of the pocket t o the t o p sur f ace of the carrier 6. pocket position rel a tive t o sprocket hole measured as true position of pocke t , not pocket hole note 4 note 4 note 5 note 6 note 1 note 6 detail a detail a 16.30 16.00 15.70 direction of feed 7.35 7.25 7.15 7.35 7.25 7.15 12.10 12.00 11.90 4.10 4.00 3.90 7.60 7.50 7.40 2.10 2.00 1.90 1.85 1.75 1.65 1.20 1.10 1.00 a a ? 1.5 ~ 1.6 ? 1.5 min top view section a-a r 0.25 0.25 0.35 0.30 0.25 figure 35 . lfcsp tape and reel outline dimensions dimensions shown in millimeters ordering guide model 1 temperature range lead finish msl rating 2 package description package option branding 3 HMC7043lp7fe ? 40 o c to +85 c nipdau msl -3 48- lead lead frame chip scale package [lfcsp] hcp -48-1 xxxx 7043 HMC7043lp7fetr ?40 o c to +85c nipdau msl -3 48- lead lead frame chip scale package [lfcsp] hcp -48-1 xxxx 7043 ek1HMC7043lp7f ? 40c to +85c evaluation kit 1 e = rohs compliant part. 2 the m aximum peak reflow temperature is 260c for the HMC7043lp7fe . 3 four - digit lot number represented by xxxx . ? 2015 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13114 - 0- 7/16(b)

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